This invention relates to a graphical user aid that may be used for migrating a circuit design from a source device into a target device. For example, programmable logic designs (PLDs or FPGAs) may be migrated into equivalent or substitute application-specific integrated circuits (“ASICs”). The invention also relates to a device selector guide for evaluating migration prospects before completing the migration.
A typical programmable logic device (“PLD”) or field-programmable gate array (“FPGA”) includes many logic elements (“LEs”) of a fixed size. (For convenience herein, the term FPGA is used as a generic term for PLDs and FPGAs.) For example, an FPGA LE may include a four-input look-up table (“LUT”), a register, and some routing circuitry that allows the register to be either used (e.g., to register the output of the LUT) if sequential logic or operation is desired, or to be bypassed by the LUT output if only combinational or combinatorial logic or operation is desired. An FPGA LE may also have other features or capabilities, but the foregoing example will be sufficiently illustrative. In addition to many LEs, an FPGA also typically has programmable routing circuitry for conveying signals to, from, and/or between the LEs in any of many different ways so that very complex and/or extensive logic or logic-type operations can be performed by combining or otherwise using multiple LEs. Also in addition to LEs, an FPGA may have other types of circuitry, such as input/output (“I/O”) circuitry, blocks of memory, microprocessors, special-purpose circuitry such as digital signal processing (“DSP”) blocks, delay locked loops (“DLL”), phase locked loops (“PLL”), high-speed serial interface (“HSSI”) blocks, etc. These other types of circuitry may also be interconnectable to one another (and to the LEs) via the above-mentioned programmable routing circuitry.
FPGAs have many advantages that are well known to those skilled in the art. In some instances, however, it may be desirable to replace the FPGA with an ASIC equivalent device so that cost can be reduced in a high-volume application. For example, a design may start out in an FPGA. But after that design has been sufficiently proven and has reached sufficiently high volume, substituting an ASIC equivalent can be very cost-effective.
One approach to providing ASIC equivalents to FPGAs employs an ASIC architecture having the same basic organization of circuit resources as the starting FPGA. For example, if the FPGA includes an array of LEs, each of which has a four-input LUT (“4-LUT”) and a register, then the ASIC has a similar array of LEs including 4-LUTs and registers. Certain layers in the ASIC are then customized to a particular user's design to effectively “program” the LEs and to provide the required interconnection routing among the LEs.
A second approach to providing ASIC equivalents of FPGAs includes circuit resources in the ASIC equivalent that are not the same as the circuit resources used in the FPGA. For example, the ASIC equivalent device may have logic elements referred to herein as hybrid logic elements (“HLEs”). Each HLE may include a relatively small, general-purpose, combinatorial logic component (e.g., a one-input LUT or “2-LUT”), a relatively small array of logic gates (e.g., two two-input NAND gates), and some associated interconnection or routing resources. The amount of operational circuitry in an HLE (e.g., the 2-LUT and the NAND gates) is much less than the amount of operational circuitry in a related FPGA LE. At least some aspects of the routing resources in an HLE are programmable (e.g., mask programmable using vias) for such purposes as making input connections to the HLE, output connections from the HLE, and internal connections within the HLE. For some relatively under-utilized FPGA LEs, one ASIC HLE can perform the functions of the LE. If an LE has greater utilization, then several adjacent (or at least nearby) HLEs may be needed to equivalently perform the LE's functions. The routing resources of HLEs facilitate interconnecting adjacent (or nearby) HLEs that need to be put together to perform any LE's functions. In any case, only as many HLEs as are necessary to perform an LE's functions are used to provide an equivalent of that LE. Because many LEs in most designs are not fully utilized, the number of HLEs provided on an ASIC for use as equivalent to an FPGA can be significantly less than the number of HLEs that would be required if all LEs were fully utilized. This is a significant ASIC size reduction as compared to an ASIC that uses a fully featured LE for each FPGA LE. Furthermore, by using HLEs or other logic elements that are not the same as the LEs in the equivalent FPGA, multiple equivalent ASIC sizes and technology families may be used as equivalents to one FPGA. Similarly, it may also be advantageous to replace or substitute other circuit resources of the FPGA with different numbers or types of circuit resources in the ASIC equivalent device.
This second approach to providing ASIC equivalents of FPGAs may result in advantages, such as, ASIC size reduction. However, like any migration of a chip design from one technology family to another, there are uncertainties as to how well the resources in the source technology will map to the resources of the destination technology. Typically, in order to resolve these uncertainties the potentially long and costly migration must actually be performed.